1. The Field of the Invention
The present invention is directed to the manufacture of integrated circuits. More particularly, the present invention is directed to shallow junctions formed on in-process integrated circuit wafers and to methods of forming the shallow junctions using plasma doping.
2. The Relevant Technology
The semiconductor industry is in the midst of a movement toward greater integrated circuit densification and miniaturization. Resulting from this movement is the development of highly compact and efficient semiconductor devices, attended by an increase in the complexity and number of such semiconductor devices that can now be successfully aggregated on a single integrated circuit wafer. These benefits have in turn resulted in the availability of more compact and efficient integrated circuits, and in the lower cost of these integrated circuits.
The greater miniaturization and densification of semiconductor devices, including resistors, capacitors, diodes, and transistors, has been achieved, in part, by a reduction in the scale of the various components of the semiconductor devices. Among the components which have been reduced in scale as part of the miniaturization and densification movement are junctions which are formed by doping silicon substrates located on integrated circuit wafers. These junctions are used to form source and drain regions of MOS transistors, among other things, and comprise regions of silicon which are doped with dopants such as boron and phosphorous. The dopants allow silicon, normally only a semiconducting material, to conduct current through the addition of either electrons or electron holes, depending on the dopant type.
Reducing the depth of a junction in the silicon substrate helps in producing an integrated circuit with a resultant high circuit density, high speed, and low power consumption, and thereby aids in the miniaturization and densification of integrated circuits.
One area of recent progress in the formation of junctions is the development of a doping process known as plasma doping, or xe2x80x9cPLAD.xe2x80x9d PLAD is a process involving the use of a plasma to assist in doping at a lower ion bombardment velocity and energy than conventional ion bombardment implantation doping processes which do not operate in a plasma. The plasma in the PLAD operation is biased with an energy relative to the silicon substrate that drives the dopants into the silicon substrate. PLAD results in a shallow doped junction that has a higher concentration of dopants than can be provided by conventional ion bombardment implantation doping processes. With PLAD processing, the shallow and heavily doped junctions allow the contacts or interconnects to be made correspondingly small. The higher concentration of dopants at the surface of the junction has an advantageous resistivity where the junction is connected to other structures through a contact or interconnect. When so doing, the shallow junction with a high concentration of dopants forms an interface with the contact or interconnect that has a lower resistivity than would be otherwise formed.
The shallow junction with a high dopant concentration formed in the PLAD process allows greater miniaturization and densification of the integrated circuit being formed, due to the capability of forming a contact or interconnect to the junction with a high degree of miniaturization and yet a low resistance interface. Nevertheless, the PLAD processes used to produce shallow junctions still exhibit certain problems.
Several of the problems encountered with PLAD processes are illustrated by the MOS transistor structure under formation in FIG. 1. FIG. 1 shows a step in the process of forming a MOS transistor structure in which a gate region 14 has been formed on a semiconductor substrate 10. Portions of semiconductor substrate 10 at the sides of gate region 14 have been doped through a gate oxide layer 12 with a PLAD process. The PLAD process has formed junctions 16 which are to serve as source and drain regions on the completed MOS transistor. Junctions 16 exhibit a high doping concentration that is relatively consistent and terminates abruptly at a bottom component 16a of each junction 16.
As PLAD is not highly selective of the atoms being driven into silicon substrate 10, heavier atoms within a carrier gas are driven into silicon substrate 10 with a greater force than dopant atoms, and are consequently driven to a greater depth. This inconsistency in depth causes a jagged unevenness to bottom component 16a of junctions 16. Junctions 16 also have a dopant concentration gradient that terminates abruptly at edges 16a. The abrupt dopant concentration gradient termination, together with unevenness of bottom component is 16a, cause an undesirable increase in reverse bias current leakage. Reverse bias current leakage causes a drain of power through the integrated circuit when finished, a problem which is at odds with the low power requirements of modem integrated circuit applications.
The abrupt dopant concentration gradient termination at bottom component 16a of junction 16 can affect yield when forming a MOS transistor, in that a high amount of dopants at a greater depth may cause bottom component 16a of junctions 16 to substantially underlap gate region 14. The underlap of junctions below the gate is caused by a process known as out diffusion. When junction underlap occurs, there is a decrease in the distance between junctions 16. The result of junction underlap is a high threshold voltage, which is the voltage required to cause the MOS transistor to conduct current. A high threshold voltage is generally undesirable in MOS transistors.
One method used in the prior art for solving the problem of excessive junction underlap has been to form polysilicon spacers on the sides of the gate region at the periphery thereof, such as spacers 18 of FIG. 2. Spacers 18 are formed by conventional processes at the edge of gate region 14 prior to PLAD. Spacers 18 further the distance between junctions 16 and prevent junction underlap below gate region 14, thus maintaining a low threshold voltage. Nevertheless, the use of spacers 18 does not solve the problems of reverse bias current leakage. The formation of spacers also adds processing steps and thus throughput time to the integrated circuit formation process.
From the above discussion, it is seen that a need exists in the art for an improved method of forming shallow junctions on semiconductor substrates. Specifically, an improved method of forming shallow junctions is needed which has the PLAD benefits of shallower junctions with higher concentrations of dopants, without the PLAD constraints of junction underlap, jagged unevenness of the bottom component of the junctions, and abrupt dopant concentration gradient termination. Such an improved method would be an aid in the continued formation of more highly miniaturized and densified integrated circuits.
The present invention seeks to resolve the above and other problems which have been experienced in the art. More particularly, the present invention constitutes an advancement in the art by providing a method of forming shallow junctions on silicon substrates of integrated circuit wafers which achieves each of the objects listed below.
It is an object of the present invention to provide a method of forming shallow, heavily doped junctions on silicon substrates of integrated circuit wafers in order to provide smaller, more efficient transistors, diodes, resistors, and other semiconductor devices.
It is another object of the present invention to provide such a method of forming shallow junctions which utilizes PLAD.
It is further an object of the present invention to provide such a method which remedies rough and jagged unevenness of the bottom component of the junctions, abrupt dopant concentration gradient termination of the junctions, and high reverse bias current leakage which result from PLAD formation of junctions.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein in the preferred embodiment, a method is provided for forming a shallow junction with a variable profile gradation of dopants.
The first step of the method of the present invention comprises providing a semiconductor wafer having a surface on which to form the shallow junction. In one embodiment, the surface comprises a silicon substrate of an in-process integrated circuit wafer and the junction being formed comprises one of a source or a drain of a MOS transistor.
A further step comprises conducting a PLAD operation to form a shallow, highly doped inner portion of the junction having a high concentration of dopants.
A further step comprises conducting a second doping operation to form a lightly doped outer portion of the junction. In one embodiment, this step comprises a conventional ion bombardment implantation doping operation with low power and low dopant dosage. The conventional ion bombardment implantation doping operation is typically conducted with a medium power implanter. The result of the conventional ion bombardment implantation doping operation is a lightly doped outer portion surrounding a heavily doped inner portion. The lightly doped outer portion has a bottom edge that is more even and straight than edges of junctions formed by PLAD. The lightly doped outer portion also has a lower concentration of dopants than the heavily doped inner portion.
Another step of the method of the present invention is to anneal the semiconductor wafer. The anneal causes a more even distribution of dopant concentration therein and helps to remove imperfections in the internal lattice structure. The anneal is an optional step that can be conducted after each doping operation, or after any of the doping operations.
The doping operation which forms a heavily doped inner portion and the doping operation which forms a lightly doped outer portion can be conducted in reverse order. This is useful in forming a thin oxide layer over the surface. One application for the thin oxide layer is as an implant barrier to the PLAD operation. When using an implant barrier, a conventional ion bombardment implantation doping operation is conducted first, and then the thin oxide layer is deposited using a process such as TEOS. The PLAD operation is then conducted through the thin oxide layer. Thus, the lightly doped outer portion is formed without the existence of the thin oxide layer, while the thin oxide layer is present to serve as an implant barrier to the PLAD operation. This use of a thin oxide layer as an implant barrier in this embodiment further reduces the depth of the dopants implanted in the PLAD operation, while maintaining the depth of the dopants implanted by the conventional ion bombardment implantation doping operation. The use of a thin oxide layer as an implant barrier also maintains the high concentration of dopants on the surface of the shallow junction in order to form a low resistance contact and interconnect interface.
The result of the method of the present invention is a shallow junction which is useful for forming diodes, resistors, and transistors. The junction has a variable profile gradation of dopants, with a first concentration of dopants in a heavily doped inner portion, and a second, lower concentration of dopants in the deeper lightly doped outer portion. The junction is also formed with an even bottom edge which, along with the variable profile gradation of dopants, helps to eliminate reverse bias current leakage. The variable profile gradation of dopants also helps to reduce underlap, and thereby helps to maintain a low threshold voltage without the need for forming spacers.
The method of the present invention has been found to be easily integrated into the manufacturing flow process and to be relatively inexpensive.